The present invention relates to memory systems and semiconductor integrated circuits and more particularly to memory systems and semiconductor integrated circuits in which the operation timings can be set externally and which they can be operated at suitable timings that systems require.
Generally, semiconductor memories in a system set are incorporated on a common board together with other semiconductor elements, such as D-A converters, A-D converters, CPUs, and control logic circuits. Likewise, in merged memory-logic devices (embedded memory devices), semiconductor memories are incorporated on a common chip together with microprocessors and control logic circuits. In the former case, the semiconductor memories are formed in a package or in the form of bare chips, whereas in the latter case, they are formed using a common process for forming other devices that are incorporated on the chip.
In bare-chip-form semiconductor memories incorporated in system set products that are not packaged products, and in merged memory-logic products fabricated with control logic circuits using the same process, it is often the case that the control logic circuit also serves the function of a circuit for generating control signals to the semiconductor memories, in order to reduce the area occupied by the circuit. In that case, the control logic circuit having the dual function supplies memory control signals to semiconductor memories at predetermined timings.
When constructing semiconductor memories on a common board or a common system with microprocessors or the like, it is necessary to select and incorporate devices that can operate at an operating speed that is required for the memory in the set as a whole.
If a plurality of semiconductor memories are incorporated in a given system, however, the control logic circuit having the dual function supplies memory control signals to two or more semiconductor memories at the same timings, and therefore, these semiconductor memories operate with the same timings and consume electric current with the same timings. Consequently, the system suffers from the drawback of large peak currents.
In addition, when power supply voltages and memory ambient temperatures of semiconductor memories varies, operation timings of the semiconductor memories change according to the variations, even though memory control signals are set to be output so that semiconductor memories in the system operate with suitable predetermined timings. Thus, the memories suffer from the drawback that timing deviations occur and the memories do not operate with the suitable predetermined timings.
Such problems of the increase in peak current and the variation in operation timings arise in merged memory-logic devices as well as in system sets.
As described above, semiconductor memories and systems incorporating these have a drawback that operation timings are fixed irrespective of operating conditions, such as simultaneous operation with other semiconductor memories, power supply voltages, and ambient temperatures. Similar drawbacks also exist in ferroelectric memories, which are non-volatile memories. In the following, drawbacks in ferroelectric memories (FeRAMs) are discussed.
First, deterioration of ferroelectric memory is discussed. When data write and rewrite are repeated in a ferroelectric memory, that is, when polarization reversals are repeated in a ferroelectric, the ferroelectric suffers a ferroelectric fatigue deterioration phenomena, in which, for example, the repetition of polarization reversal causes remanent polarization to decrease. Because the ferroelectric memory is a destructive readout memory, the ferroelectric fatigue deterioration phenomena occur as the ferroelectric undergoes polarization reversals both during write operation and during read operation, resulting in reliability problems, such as a decrease in data retention duration, readout incapability, and rewrite incapability. In the endurance deterioration, which is one of the ferroelectric fatigue deterioration phenomena, the degree of deterioration depends on the voltage applied to memory cells during data writing and the time during which the voltage is applied, so the deterioration is promoted as the voltage is higher and the time during which the voltage is applied is longer whereas the deterioration phenomenon is suppressed as the write voltage is lower and the time during which the voltage is applied is shorter. However, in such write operation, because the operation timings are predetermined and the data write time is fixed, it is often the case that stress is excessively applied to memory cells and thus ferroelectric fatigue deterioration phenomena are promoted, which is undesirable in terms of reliability.
Concerning prior art ferroelectric memories, Japanese Unexamined Patent Publication No. 3-113889, for example, discloses a technique of suppressing the endurance deterioration by reducing the voltage applied to the memory cells during read operations. In addition, Japanese Unexamined Patent Publication No. 3-5996 proposes a technique of operating a ferroelectric memory as a DRAM (volatile memory) during normal data-storing operations by switching the voltage applied to the memory cells during read operations between a high voltage and a low voltage. These conventional techniques, however, have such drawbacks as follows. First, an increase in layout area is caused because multiple power supply voltages need to be adopted in the semiconductor memory. Second, accuracy of applied voltages to memory cells degrades due to variation in transistor performance, and voltage reduction effect with respect to endurance deterioration vary between production lots. Third, readout defects easily occur due to shortage of the amount of readout charges.